System Verilog List of Topics

  1. Verilog to System Verilog Growth Chart

  2. Value Sets

  3. Port Declarations and Connections

  4. Data Types

  5. Compiler Directives

  6. Simulation

  7. Simple Testbench

  8. Arrays

  9. Queues

  10. Choosing Between the array types

  11. Array manipulation methods

  12. Parameters and Constants

  13. User Defined Data Types

  14. Structures

  15. Unions

  16. Strings

  17. Enumerated Data Types

  18. Casting

  19. Events

  20. Hierarchical References

  21. Programming Statements

  22. Procedural Blocks

  23. Procedural Statements and Flow Control

  24. Operators

  25. Processes

  26. Tasks and Functions

  27. Packages

  28. $Unit Scope

  29. SV Event Queue

  30. Inter process Communication

  31. Program Block

  32. Interface

  33. Verification Constructs

  34. Object Oriented Programming

  35. Randomization and Constraints

  36. Virtual Interface

  37. Coverage

  38. Call-backs

  39. Assertions

  40. Test bench Structure

  41. Other Miscellaneous Topics

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